FIG. 4 shows a sense amplifier in an MRAM proposed in R. Scheuerlein, et al., “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in Each Cell,” IEEE ISSCC Digest of Technical Papers, pp. 128–129, February 2000. The MRAM in Scheuerlein et al., uses magnetic memory cells MC, each including an MTJ element 1 and an access transistor (N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), TN1. The MTJ element 1 is connected to a bit line BLT, and connected in series to the access transistor TN1 that is turned on in response to a word line WL.
On the other hand, each of reference magnetic memory cells RefMC is connected to a complementary bit line BLC. The magnetic memory cell RefMC includes an MTJ element 2 and an access transistor TN2. The MTJ element 2 is connected to the complementary bit line BLC, and connected in series to the access transistor TN2 that is turned on in response to a reference word line RefWL. The MTJ element 1 is for data storage, whereas the MTJ element 2 is for reference.
The bit line pair BLT and BLC are connected to a sense amplifier 5 via a bit switch (also called a column switch or column select gate) 4. The bit switch 4 includes N-channel MOS transistors TN3 and TN4 that are turned on in response to a column select signal CS from a column decoder (not shown). The sense amplifier 5 senses and amplifies the electric potential difference between the bit lines BLT and BLC.
A clamp circuit 6 is connected between the bit switch 4 and the sense amplifier 5 in order to prevent the application of a voltage, equal to or higher than the breakdown voltage, across the MTJ elements 1 and 2, and minimize the bias voltage dependence of tunneling magneto-resistance (TMR), that is, the phenomenon that TMR and its ratio of change decrease depending on the bias voltage. The clamp circuit 6 includes N-channel MOS transistors TN5 and TN6 that receive a constant bias voltage Vbias to clamp the voltage across the MTJ elements 1 and 2 at a predetermined voltage (=bias voltage Vbias−threshold voltage Vth of the transistors TN5 and TN6).
In the sense amplifier 5, constant currents always flow from constant current sources 7a and 7b into resistor elements 8a and 8b, respectively. Therefore, when the bit switch 4 is off, no potential difference appears between output nodes NO1 and NO2.
Then, when the access transistors TN1 and TN2 are turned on in response to the word line WL and the reference word line RefWL, and the bit switch 4 is turned on in response to the column select signal CS for the purpose of reading data from the magnetic memory cell MC, sense currents flow through the MTJ elements 1 and 2, respectively. Since the MTJ element 1 has a resistor value R1 different from a resistor value R2 of the MTJ element 2 while the resistor elements 8a and 8b have the same resistor value ZL, a sensed potential difference |OUT−OUTN| appears between the output nodes NO1 and NO2. This potential difference is amplified by a current-mirror amplifier 9.
In such a sense amplifier 5, the constant current sources 7a, 7b, the resistor elements 8a, 8b, and the amplifier 9 consume DC currents. A bias voltage generation circuit to generate the bias voltage Vbias, not shown, also consumes DC current. Since these DC currents continue to flow as long as power is supplied to the MRAM even during standby state where the MRAM waits ready for its activation, the DC current consumption is not negligible in the field of portable devices that is considered to be an important area of application of MRAMs.
Further, the current-mirror amplifier 9 outputs a intermediate potential so that another amplifier needs to be provided at a later stage after the current-mirror amplifier 9. In addition, direct or pass-through current flows from the power supply to the ground in the post-amplifier, that is, the amplifier provided at a later stage after the current-mirror amplifier 9.